Mechanism to accelerate graphics workloads in a multi-core computing architecture

ABSTRACT

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

RELATED APPLICATION

The present application is a continuation of and claims the benefit ofSer. No. 17/322,146, filed May 17, 2021, issued on Sep. 13, 2022 as U.S.Pat. No. 11,443,405, which is a continuation of U.S. patent applicationSer. No. 16/255,721, filed on Jan. 23, 2019, issued on May 18, 2021 asU.S. Pat. No. 11,010,858 and entitled “MECHANISM TO ACCELERATE GRAPHICSWORKLOADS IN A MULTI-CORE COMPUTING ARCHITECTURE”, which is acontinuation of U.S. Pat. No. 10,229,470, issued on Mar. 12, 2019, whichis incorporated by reference in its entirety.

FIELD

Embodiments described herein generally relate to computers. Moreparticularly, embodiments are described for accelerating execution ofgraphics workloads at computing devices.

BACKGROUND

Graphics processing involves a performance of rapid mathematicalcalculations for image rendering. Such graphics workloads may beperformed at a general-purpose microprocessor or a graphics processingunit (GPU), which is a specialized electronic circuit, to rapidlymanipulate and alter memory to accelerate the creation of images in aframe buffer intended for output to a display.

Various acceleration techniques (e.g., software and fixed functionunits) are currently implemented at microprocessors and GPUs. However,such techniques have limitations and/or disadvantages. An improvement onthese techniques features implementation of a field-programmable gatearray (FPGA) to accelerate the execution of performance critical loopsin order to free up processing core resources. Such an implementation isan improvement because FPGAs are more performance and power efficient inexecuting the loops (e.g., they are not limited to a core's data access,instruction set architecture (ISA) and microarchitecture limitations).In this design, a single FPGA is shared by all microprocessors or GPUcores. The shared design continues to have performance deficiencies,however, since the single FPGA is a contended resource that has toservice different cores needing access for synchronization.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example, and not by way oflimitation, in the figures of the accompanying drawings in which likereference numerals refer to similar elements.

FIG. 1 is a block diagram of a processing system, according to anembodiment.

FIG. 2 is a block diagram of an embodiment of a processor having one ormore processor cores, an integrated memory controller, and an integratedgraphics processor.

FIG. 3 is a block diagram of a graphics processor, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores.

FIG. 4 is a block diagram of a graphics processing engine of a graphicsprocessor in accordance with some embodiments.

FIG. 5 is a block diagram of another embodiment of a graphics processor.

FIG. 6 illustrates thread execution logic including an array ofprocessing elements employed in some embodiments of a graphicsprocessing engine.

FIG. 7 is a block diagram illustrating graphics processor instructionformats according to some embodiments.

FIG. 8 is a block diagram of another embodiment of a graphics processor.

FIG. 9A is a block diagram illustrating a graphics processor commandformat according to an embodiment and FIG. 9B is a block diagramillustrating a graphics processor command sequence according to anembodiment.

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system according to some embodiments.

FIG. 11 is a block diagram illustrating an IP core development systemthat may be used to manufacture an integrated circuit to performoperations according to an embodiment.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment.

FIG. 13 is a block diagram illustrating an exemplary graphics processorof a system on a chip integrated circuit that may be fabricated usingone or more IP cores, according to an embodiment.

FIG. 14 is a block diagram illustrating an additional exemplary graphicsprocessor of a system on a chip integrated circuit that may befabricated using one or more IP cores, according to an embodiment.

FIG. 15 illustrates one embodiment of a computing device.

FIG. 16A & FIG. 16B illustrate embodiments of graphics processing coreswith local FPGAs.

FIGS. 17A & FIG. 17B illustrate embodiments of graphics processing coreshaving a local FPGA.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth.However, embodiments, as described herein, may be practiced withoutthese specific details. In other instances, well-known circuits,structures and techniques have not been shown in details in order not toobscure the understanding of this description.

Embodiments provide for an FPGA coupled to each processing core includedin a general-purpose microprocessor and/or GPU to accelerate executionof performance critical loops and free up resources on a processor core.In such embodiments, each core may include a small FPGA to enable thecore to select a workload kernel to accelerate. Thus, an FPGA perprocessor core enables FPGAs to be quickly reprogrammable for theefficient exchange of FPGA programs/implementations during the lifetimeof a workload. In other embodiments, a set of one or more FPGAs may beassigned to simultaneously handle different tasks, enabling one or moreFPGAs to be programmed to execute different kernels.

It is contemplated that terms like “request”, “query”, “job”, “work”,“work item”, and “workload” may be referenced interchangeably throughoutthis document. Similarly, an “application” or “agent” may refer to orinclude a computer program, a software application, a game, aworkstation application, etc., offered through an API, such as a freerendering API, such as Open Graphics Library (OpenGL®), DirectX® 11,DirectX® 12, etc., where “dispatch” may be interchangeably referred toas “work unit” or “draw” and similarly, “application” may beinterchangeably referred to as “workflow” or simply “agent”. Forexample, a workload, such as that of a 3D game, may include and issueany number and type of “frames” where each frame may represent an image(e.g., sailboat, human face). Further, each frame may include and offerany number and type of work units, where each work unit may represent apart (e.g., mast of sailboat, forehead of human face) of the image(e.g., sailboat, human face) represented by its corresponding frame.However, for the sake of consistency, each item may be referenced by asingle term (e.g., “dispatch”, “agent”, etc.) throughout this document.

In some embodiments, terms like “display screen” and “display surface”may be used interchangeably referring to the visible portion of adisplay device while the rest of the display device may be embedded intoa computing device, such as a smartphone, a wearable device, etc. It iscontemplated and to be noted that embodiments are not limited to anyparticular computing device, software application, hardware component,display device, display screen or surface, protocol, standard, etc. Forexample, embodiments may be applied to and used with any number and typeof real-time applications on any number and type of computers, such asdesktops, laptops, tablet computers, smartphones, head-mounted displaysand other wearable devices, and/or the like. Further, for example,rendering scenarios for efficient performance using this novel techniquemay range from simple scenarios, such as desktop compositing, to complexscenarios, such as 3D games, augmented reality applications, etc.

System Overview

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. In various embodiments the system 100 includes one or moreprocessors 102 and one or more graphics processors 108, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 102 or processorcores 107. In one embodiment, the system 100 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

An embodiment of system 100 can include, or be incorporated within aserver-based gaming platform, a game console, including a game and mediaconsole, a mobile gaming console, a handheld game console, or an onlinegame console. In some embodiments system 100 is a mobile phone, smartphone, tablet computing device or mobile Internet device. Dataprocessing system 100 can also include, couple with, or be integratedwithin a wearable device, such as a smart watch wearable device, smarteyewear device, augmented reality device, or virtual reality device. Insome embodiments, data processing system 100 is a television or set topbox device having one or more processors 102 and a graphical interfacegenerated by one or more graphics processors 108.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 107 is configured to process aspecific instruction set 109. In some embodiments, instruction set 109may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 107 may each process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 is additionally includedin processor 102 which may include different types of registers forstoring different types of data (e.g., integer registers, floating pointregisters, status registers, and an instruction pointer register). Someregisters may be general-purpose registers, while other registers may bespecific to the design of the processor 102.

In some embodiments, processor 102 is coupled to a processor bus 110 totransmit communication signals such as address, data, or control signalsbetween processor 102 and other components in system 100. In oneembodiment the system 100 uses an exemplary ‘hub’ system architecture,including a memory controller hub 116 and an Input Output (I/O)controller hub 130. A memory controller hub 116 facilitatescommunication between a memory device and other components of system100, while an I/O Controller Hub (ICH) 130 provides connections to I/Odevices via a local I/O bus. In one embodiment, the logic of the memorycontroller hub 116 is integrated within the processor.

Memory device 120 can be a dynamic random access memory (DRAM) device, astatic random access memory (SRAM) device, flash memory device,phase-change memory device, or some other memory device having suitableperformance to serve as process memory. In one embodiment the memorydevice 120 can operate as system memory for the system 100, to storedata 122 and instructions 121 for use when the one or more processors102 executes an application or process. Memory controller hub 116 alsocouples with an optional external graphics processor 112, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations.

In some embodiments, ICH 130 enables peripherals to connect to memorydevice 120 and processor 102 via a high-speed I/O bus. The I/Operipherals include, but are not limited to, an audio controller 146, afirmware interface 128, a wireless transceiver 126 (e.g., Wi-Fi,Bluetooth), a data storage device 124 (e.g., hard disk drive, flashmemory, etc.), and a legacy I/O controller 140 for coupling legacy(e.g., Personal System 2 (PS/2)) devices to the system. One or moreUniversal Serial Bus (USB) controllers 142 connect input devices, suchas keyboard and mouse 144 combinations. A network controller 134 mayalso couple to ICH 130. In some embodiments, a high-performance networkcontroller (not shown) couples to processor bus 110. It will beappreciated that the system 100 shown is exemplary and not limiting, asother types of data processing systems that are differently configuredmay also be used. For example, the I/O controller hub 130 may beintegrated within the one or more processor 102, or the memorycontroller hub 116 and I/O controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 112.

FIG. 2 is a block diagram of an embodiment of a processor 200 having oneor more processor cores 202A-202N, an integrated memory controller 214,and an integrated graphics processor 208. Those elements of FIG. 2having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor200 can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of processor cores202A-202N includes one or more internal cache units 204A-204N. In someembodiments each processor core also has access to one or more sharedcached units 206.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more Peripheral Component Interconnect buses (e.g., PCI, PCIExpress). System agent core 210 provides management functionality forthe various processor components. In some embodiments, system agent core210 includes one or more integrated memory controllers 214 to manageaccess to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, a displaycontroller 211 is coupled with the graphics processor 208 to drivegraphics processor output to one or more coupled displays. In someembodiments, display controller 211 may be a separate module coupledwith the graphics processor via at least one interconnect, or may beintegrated within the graphics processor 208 or system agent core 210.

In some embodiments, a ring-based interconnect 212 is used to couple theinternal components of the processor 200. However, an alternativeinterconnect unit may be used, such as a point-to-point interconnect, aswitched interconnect, or other techniques, including techniques wellknown in the art. In some embodiments, graphics processor 208 coupleswith the ring-based interconnect 212 via an I/O link 213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202-202N and graphicsprocessor 208 use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-N executea first instruction set, while at least one of the other cores executesa subset of the first instruction set or a different instruction set. Inone embodiment processor cores 202A-202N are heterogeneous in terms ofmicroarchitecture, where one or more cores having a relatively higherpower consumption couple with one or more power cores having a lowerpower consumption. Additionally, processor 200 can be implemented on oneor more chips or as an SoC integrated circuit having the illustratedcomponents, in addition to other components.

FIG. 3 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 300 includes amemory interface 314 to access memory. Memory interface 314 can be aninterface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. In some embodiments, graphics processor 300 includesa video codec engine 306 to encode, decode, or transcode media to, from,or between one or more media encoding formats, including, but notlimited to Moving Picture Experts Group (MPEG) formats such as MPEG-2,Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well asthe Society of Motion Picture & Television Engineers (SMPTE) 424M/VC-1,and Joint Photographic Experts Group (JPEG) formats such as JPEG, andMotion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, graphics processing engine 310 is a compute engine forperforming graphics operations, including three-dimensional (3D)graphics operations and media operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

3D/Media Processing

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the GPE 410 is a version of the GPE 310 shown in FIG. 3 .Elements of FIG. 4 having the same reference numbers (or names) as theelements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such. For example, the 3D pipeline 312 and media pipeline 316 of FIG.3 are illustrated. The media pipeline 316 is optional in someembodiments of the GPE 410 and may not be explicitly included within theGPE 410.

In some embodiments, GPE 410 couples with a command streamer 403, whichprovides a command stream to the GPE 3D pipeline 312 and media pipelines316. In some embodiments, command streamer 403 is coupled to memory,which can be system memory, or one or more of internal cache memory andshared cache memory. In some embodiments, command streamer 403 receivescommands from the memory and sends the commands to 3D pipeline 312and/or media pipeline 316. The commands are directives fetched from aring buffer, which stores commands for the 3D pipeline 312 and mediapipeline 316. In one embodiment, the ring buffer can additionallyinclude batch command buffers storing batches of multiple commands. The3D pipeline 312 and media pipeline 316 process the commands byperforming operations via logic within the respective pipelines or bydispatching one or more execution threads to an execution unit array(graphics core array 414). In some embodiments, graphics core array 414is scalable, such that the array includes a variable number of executionunits based on the target power and performance level of GPE 410.

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420.

Execution Units

FIG. 5 is a block diagram of another embodiment of a graphics processor500. Elements of FIG. 5 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 500 includes a ring interconnect502, a pipeline front-end 504, a media engine 537, and graphics cores580A-580N. In some embodiments, ring interconnect 502 couples thegraphics processor to other processing units, including other graphicsprocessors or one or more general-purpose processor cores. In someembodiments, the graphics processor is one of many processors integratedwithin a multi-core processing system.

In some embodiments, graphics processor 500 receives batches of commandsvia ring interconnect 502. The incoming commands are interpreted by acommand streamer 503 in the pipeline front-end 504. In some embodiments,graphics processor 500 includes scalable execution logic to perform 3Dgeometry processing and media processing via the graphics core(s)580A-580N. For 3D geometry processing commands, command streamer 503supplies commands to geometry pipeline 536. For at least some mediaprocessing commands, command streamer 503 supplies the commands to avideo front-end 534, which couples with a media engine 537. In someembodiments, media engine 537 includes a Video Quality Engine (VQE) 530for video and image post-processing and a multi-format encode/decode(MFX) 533 engine to provide hardware-accelerated media data encode anddecode. In some embodiments, geometry pipeline 536 and media engine 537each generate execution threads for the thread execution resourcesprovided by at least one graphics core 580A.

In some embodiments, graphics processor 500 includes scalable threadexecution resources featuring modular cores 580A-580N (sometimesreferred to as core slices), each having multiple sub-cores 550A-550N,560A-560N (sometimes referred to as core sub-slices). In someembodiments, graphics processor 500 can have any number of graphicscores 580A through 580N. In some embodiments, graphics processor 500includes a graphics core 580A having at least a first sub-core 550A anda second core sub-core 560A. In other embodiments, the graphicsprocessor is a low power processor with a single sub-core (e.g., 550A).In some embodiments, graphics processor 500 includes multiple graphicscores 580A-580N, each including a set of first sub-cores 550A-550N and aset of second sub-cores 560A-560N. Each sub-core in the set of firstsub-cores 550A-550N includes at least a first set of execution units552A-552N and media/texture samplers 554A-554N. Each sub-core in the setof second sub-cores 560A-560N includes at least a second set ofexecution units 562A-562N and samplers 564A-564N. In some embodiments,each sub-core 550A-550N, 560A-560N shares a set of shared resources570A-570N. In some embodiments, the shared resources include sharedcache memory and pixel operation logic. Other shared resources may alsobe included in the various embodiments of the graphics processor.

FIG. 6 illustrates thread execution logic 600 including an array ofprocessing elements employed in some embodiments of a GPE. Elements ofFIG. 6 having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

In some embodiments, thread execution logic 600 includes a pixel shader602, a thread dispatcher 604, instruction cache 606, a scalableexecution unit array including a plurality of execution units 608A-608N,a sampler 610, a data cache 612, and a data port 614. In one embodimentthe included components are interconnected via an interconnect fabricthat links to each of the components. In some embodiments, threadexecution logic 600 includes one or more connections to memory, such assystem memory or cache memory, through one or more of instruction cache606, data port 614, sampler 610, and execution unit array 608A-608N. Insome embodiments, each execution unit (e.g. 608A) is an individualvector processor capable of executing multiple simultaneous threads andprocessing multiple data elements in parallel for each thread. In someembodiments, execution unit array 608A-608N includes any numberindividual execution units.

In some embodiments, execution unit array 608A-608N is primarily used toexecute “shader” programs. In some embodiments, the execution units inarray 608A-608N execute an instruction set that includes native supportfor many standard 3D graphics shader instructions, such that shaderprograms from graphics libraries (e.g., Direct 3D and OpenGL) areexecuted with a minimal translation. The execution units support vertexand geometry processing (e.g., vertex programs, geometry programs,vertex shaders), pixel processing (e.g., pixel shaders, fragmentshaders) and general-purpose processing (e.g., compute and mediashaders).

Each execution unit in execution unit array 608A-608N operates on arraysof data elements. The number of data elements is the “execution size,”or the number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-608N support integer andfloating-point data types.

The execution unit instruction set includes single instruction multipledata (SIMD) instructions. The various data elements can be stored as apacked data type in a register and the execution unit will process thevarious elements based on the data size of the elements. For example,when operating on a 256-bit wide vector, the 256 bits of the vector arestored in a register and the execution unit operates on the vector asfour separate 64-bit packed data elements (Quad-Word (QW) size dataelements), eight separate 32-bit packed data elements (Double Word (DW)size data elements), sixteen separate 16-bit packed data elements (Word(W) size data elements), or thirty-two separate 8-bit data elements(byte (B) size data elements). However, different vector widths andregister sizes are possible.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, sampler 610 is included to provide texture sampling for 3Doperations and media sampling for media operations. In some embodiments,sampler 610 includes specialized texture or media sampling functionalityto process texture or media data during the sampling process beforeproviding the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. In some embodiments, thread execution logic 600includes a local thread dispatcher 604 that arbitrates thread initiationrequests from the graphics and media pipelines and instantiates therequested threads on one or more execution units 608A-608N. For example,the geometry pipeline (e.g., 536 of FIG. 5 ) dispatches vertexprocessing, tessellation, or geometry processing threads to threadexecution logic 600 (FIG. 6 ). In some embodiments, thread dispatcher604 can also process runtime thread spawning requests from the executingshader programs.

Once a group of geometric objects has been processed and rasterized intopixel data, pixel shader 602 is invoked to further compute outputinformation and cause results to be written to output surfaces (e.g.,color buffers, depth buffers, stencil buffers, etc.). In someembodiments, pixel shader 602 calculates the values of the variousvertex attributes that are to be interpolated across the rasterizedobject. In some embodiments, pixel shader 602 then executes anapplication programming interface (API)-supplied pixel shader program.To execute the pixel shader program, pixel shader 602 dispatches threadsto an execution unit (e.g., 608A) via thread dispatcher 604. In someembodiments, pixel shader 602 uses texture sampling logic in sampler 610to access texture data in texture maps stored in memory. Arithmeticoperations on the texture data and the input geometry data compute pixelcolor data for each geometric fragment, or discards one or more pixelsfrom further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 output processed data tomemory for processing on a graphics processor output pipeline. In someembodiments, the data port 614 includes or couples to one or more cachememories (e.g., data cache 612) to cache data for memory access via thedata port.

FIG. 7 is a block diagram illustrating graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments, theinstruction formats 700 described and illustrated aremacro-instructions, in that they are instructions supplied to theexecution unit, as opposed to micro-operations resulting frominstruction decode once the instruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit format 710. A 64-bit compactedinstruction format 730 is available for some instructions based on theselected instruction, instruction options, and number of operands. Thenative 128-bit format 710 provides access to all instruction options,while some options and operations are restricted in the 64-bitinstruction format 730. The native instructions available in the 64-bitinstruction format 730 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 713. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit format 710.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). For 128-bitinstructions 710 an exec-size field 716 limits the number of datachannels that will be executed in parallel. In some embodiments,exec-size field 716 is not available for use in the 64-bit compactinstruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 722, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode information 726 specifying, for example, whetherdirect register addressing mode or indirect register addressing mode isused. When direct register addressing mode is used, the register addressof one or more operands is directly provided by bits in the instruction710.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode todefine a data access alignment for the instruction. Some embodimentssupport access modes including a 16-byte aligned access mode and a1-byte aligned access mode, where the byte alignment of the access modedetermines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction 710 may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction 710 may use 16-byte-aligned addressing for allsource and destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction 710 directly provide the register address of one ormore operands. When indirect register addressing mode is used, theregister address of one or more operands may be computed based on anaddress register value and an address immediate field in theinstruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (imp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a graphics pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of graphics pipeline 820 or media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A, 852B via a thread dispatcher831.

In some embodiments, execution units 852A, 852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A, 852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, graphics pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to graphics pipeline 820. Insome embodiments, if tessellation is not used, tessellation components811, 813, 817 can be bypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A, 852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into theirper pixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer 873 and access un-rasterizedvertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A, 852B and associated cache(s) 851,texture and media sampler 854, and texture/sampler cache 858interconnect via a data port 856 to perform memory access andcommunicate with render output pipeline components of the processor. Insome embodiments, sampler 854, caches 851, 858 and execution units 852A,852B each have separate memory access paths.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front-end 834. In some embodiments, videofront-end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, graphics pipeline 820 and media pipeline 830 areconfigurable to perform operations based on multiple graphics and mediaprogramming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL) and Open Computing Language (OpenCL)from the Khronos Group, the Direct3D library from the MicrosoftCorporation, or support may be provided to both OpenGL and D3D. Supportmay also be provided for the Open Source Computer Vision Library(OpenCV). A future API with a compatible 3D pipeline would also besupported if a mapping can be made from the pipeline of the future APIto the pipeline of the graphics processor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a targetclient 902 of the command, a command operation code (opcode) 904, andthe relevant data 906 for the command. A sub-opcode 905 and a commandsize 908 are also included in some commands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 904 and, if present, sub-opcode 905 to determine theoperation to perform. The client unit performs the command usinginformation in data field 906. For some commands an explicit commandsize 908 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 9B shows an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command is 912 is requiredimmediately before a pipeline switch via the pipeline select command913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, commands for the return buffer state 916 are usedto configure a set of return buffers for the respective pipelines towrite data. Some pipeline operations require the allocation, selection,or configuration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments,configuring the graphics processor also uses one or more return buffersto store output data and to perform cross thread communication. In someembodiments, the return buffer state 916 includes selecting the size andnumber of return buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930, or the media pipeline 924 beginning at themedia pipeline state 940.

The commands for the 3D pipeline state 930 include 3D state settingcommands for vertex buffer state, vertex element state, constant colorstate, depth buffer state, and other state variables that are to beconfigured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based the particular 3DAPI in use. In some embodiments, 3D pipeline state 930 commands are alsoable to selectively disable or bypass certain pipeline elements if thoseelements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of media pipeline state commands940 are dispatched or placed into in a command queue before the mediaobject commands 942. In some embodiments, commands for the mediapipeline state 940 include data to configure the media pipeline elementsthat will be used to process the media objects. This includes data toconfigure the video decode and video encode logic within the mediapipeline, such as encode or decode format. In some embodiments, commandsfor the media pipeline state 940 also support the use one or morepointers to “indirect” state elements that contain a batch of statesettings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 1014 in a machinelanguage suitable for execution by the general-purpose processor core1034. The application also includes graphics objects 1016 defined byvertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API or the OpenGL API. When theDirect3D API is in use, the operating system 1020 uses a front-endshader compiler 1024 to compile any shader instructions 1012 in HLSLinto a lower-level shader language. The compilation may be ajust-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11 is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3rdparty fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-14 illustrate exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. The exemplary integrated circuitincludes one or more application processors 1205 (e.g., CPUs), at leastone graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.The integrated circuit includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I²S/I²C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

Additionally, other logic and circuits may be included in the processorof integrated circuit 1200, including additional graphicsprocessors/cores, peripheral interface controllers, or general purposeprocessor cores.

FIG. 13 is a block diagram illustrating an exemplary graphics processor1310 of a system on a chip integrated circuit that may be fabricatedusing one or more IP cores, according to an embodiment. Graphicsprocessor 1310 can be a variant of the graphics processor 1210 of FIG.12 . Graphics processor 1310 includes a vertex processor 1305 and one ormore fragment processor(s) 1315A-1315N. Graphics processor 1310 canexecute different shader programs via separate logic, such that thevertex processor 1305 is optimized to execute operations for vertexshader programs, while the one or more fragment processor(s) 1315A-1315Nexecute fragment (e.g., pixel) shading operations for fragment or pixelshader programs. The vertex processor 1305 performs the vertexprocessing stage of the 3D graphics pipeline and generates primitivesand vertex data. The fragment processor(s) 1315A-1315N use the primitiveand vertex data generated by the vertex processor 1305 to produce aframe buffer that is displayed on a display device. In one embodiment,the fragment processor(s) 1315A-1315N are optimized to execute fragmentshader programs as provided for in the OpenGL API, which may be used toperform similar operations as a pixel shader program as provided for inthe Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for graphics processor 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1320A-1320B. In one embodiment the one or more MMU(s)1325A-1325B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 12 , such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

FIG. 14 is a block diagram illustrating an additional exemplary graphicsprocessor 1410 of a system on a chip integrated circuit that may befabricated using one or more IP cores, according to an embodiment.Graphics processor 1410 can be a variant of the graphics processor 1210of FIG. 12 . Graphics processor 1410 includes the one or more MMU(s)1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330Bof the graphics processor 1310 of FIG. 13 .

Graphics processor 1410 includes one or more shader core(s) 1415A-1415N,which provides for a unified shader core architecture in which a singlecore or type or core can execute all types of programmable shader code,including vertex shaders, fragment shaders, and compute shaders. Theexact number of shader cores present can vary among embodiments andimplementations. Additionally, graphics processor 1410 includes aninter-core task manager 1405, which acts as a thread dispatcher todispatch execution threads to one or more shader core(s) 1415A-1415N anda tiling unit 1418 to accelerate tiling operations for tile-basedrendering, in which rendering operations for a scene are subdivided inimage space, for example to exploit local spatial coherence within ascene or to optimize use of internal caches.

FIG. 15 illustrates a computing device 1500 according to one embodiment.Computing device 1500 (e.g., smart wearable devices, virtual reality(VR) devices, head-mounted display (HMDs), mobile computers, Internet ofThings (IoT) devices, laptop computers, desktop computers, servercomputers, etc.) may be the same as data processing system 100 of FIG. 1and accordingly, for brevity, clarity, and ease of understanding, manyof the details stated above with reference to FIGS. 1-14 are not furtherdiscussed or repeated hereafter.

Throughout the document, the term “user” may be interchangeably referredto as “viewer”, “observer”, “person”, “individual”, “end-user”, and/orthe like. It is to be noted that throughout this document, terms like“graphics domain” may be referenced interchangeably with “graphicsprocessing unit”, “graphics processor”, or simply “GPU” and similarly,“CPU domain” or “host domain” may be referenced interchangeably with“computer processing unit”, “application processor”, or simply “CPU”.

Computing device 1500 may include any number and type of communicationdevices, such as large computing systems, such as server computers,desktop computers, etc., and may further include set-top boxes (e.g.,Internet-based cable television set-top boxes, etc.), global positioningsystem (GPS)-based devices, etc. Computing device 1500 may includemobile computing devices serving as communication devices, such ascellular phones including smartphones, personal digital assistants(PDAs), tablet computers, laptop computers, e-readers, smarttelevisions, television platforms, wearable devices (e.g., glasses,watches, bracelets, smartcards, jewelry, clothing items, etc.), mediaplayers, etc. For example, in one embodiment, computing device 1500 mayinclude a mobile computing device employing a computer platform hostingan integrated circuit (“IC”), such as system on a chip (“SoC” or “SOC”),integrating various hardware and/or software components of computingdevice 1500 on a single chip.

As illustrated, in one embodiment, computing device 1500 may include anynumber and type of hardware and/or software components, such as (withoutlimitation) graphics processing unit 1514, graphics driver (alsoreferred to as “GPU driver”, “graphics driver logic”, “driver logic”,user-mode driver (UMD), UMD, user-mode driver framework (UMDF), UMDF, orsimply “driver”) 1516, central processing unit 1512, memory 1508,network devices, drivers, or the like, as well as input/output (I/O)sources 1504, such as touchscreens, touch panels, touch pads, virtual orregular keyboards, virtual or regular mice, ports, connectors, etc.Computing device 1500 may include operating system (OS) 1506 serving asan interface between hardware and/or physical resources of the computingdevice 1500 and a user. It is contemplated that CPU 1512 may include oneor processors, such as processor(s) 102 of FIG. 1 , while GPU 1514 mayinclude one or more graphics processors, such as graphics processor(s)108 of FIG. 1 .

It is to be noted that terms like “node”, “computing node”, “server”,“server device”, “cloud computer”, “cloud server”, “cloud servercomputer”, “machine”, “host machine”, “device”, “computing device”,“computer”, “computing system”, and the like, may be usedinterchangeably throughout this document. It is to be further noted thatterms like “application”, “software application”, “program”, “softwareprogram”, “package”, “software package”, and the like, may be usedinterchangeably throughout this document. Also, terms like “job”,“input”, “request”, “message”, and the like, may be used interchangeablythroughout this document.

It is contemplated and as further described with reference to FIGS. 1-14, some processes of the graphics pipeline as described above areimplemented in software, while the rest are implemented in hardware. Agraphics pipeline may be implemented in a graphics coprocessor design,where CPU 1512 is designed to work with GPU 1514 which may be includedin or co-located with CPU 1512. In one embodiment, GPU 1514 may employany number and type of conventional software and hardware logic toperform the conventional functions relating to graphics rendering aswell as novel software and hardware logic to execute any number and typeof instructions, such as instructions 121 of FIG. 1 , to perform thevarious novel functions as disclosed throughout this document.

As aforementioned, memory 1508 may include a random access memory (RAM)comprising application database having object information. A memorycontroller hub, such as memory controller hub 116 of FIG. 1 , may accessdata in the RAM and forward it to GPU 1514 for graphics pipelineprocessing. RAM may include double data rate RAM (DDR RAM), extendeddata output RAM (EDO RAM), etc. CPU 1512 interacts with a hardwaregraphics pipeline, as illustrated with reference to FIG. 3 , to sharegraphics pipelining functionality. Processed data is stored in a bufferin the hardware graphics pipeline, and state information is stored inmemory 1508. The resulting image is then transferred to I/O sources1504, such as a display component, such as display device 320 of FIG. 3, for displaying of the image. It is contemplated that the displaydevice may be of various types, such as Cathode Ray Tube (CRT), ThinFilm Transistor (TFT), Liquid Crystal Display (LCD), Organic LightEmitting Diode (OLED) array, etc., to display information to a user.

Memory 1508 may comprise a pre-allocated region of a buffer (e.g., framebuffer); however, it should be understood by one of ordinary skill inthe art that the embodiments are not so limited, and that any memoryaccessible to the lower graphics pipeline may be used. Computing device1500 may further include input/output (I/O) control hub (ICH) 130 asreferenced in FIG. 1 , one or more I/O sources 1504, etc.

CPU 1512 may include one or more processors to execute instructions inorder to perform whatever software routines the computing systemimplements. The instructions frequently involve some sort of operationperformed upon data. Both data and instructions may be stored in systemmemory 1508 and any associated cache. Cache is typically designed tohave shorter latency times than system memory 1508; for example, cachemight be integrated onto the same silicon chip(s) as the processor(s)and/or constructed with faster static RAM (SRAM) cells whilst the systemmemory 1508 might be constructed with slower dynamic RAM (DRAM) cells.By tending to store more frequently used instructions and data in thecache as opposed to the system memory 1508, the overall performanceefficiency of computing device 1500 improves. It is contemplated that insome embodiments, GPU 1514 may exist as part of CPU 1512 (such as partof a physical CPU package) in which case, memory 1508 may be shared byCPU 1512 and GPU 1514 or kept separated.

System memory 1508 may be made available to other components within thecomputing device 1500. For example, any data (e.g., input graphics data)received from various interfaces to the computing device 1500 (e.g.,keyboard and mouse, printer port, Local Area Network (LAN) port, modemport, etc.) or retrieved from an internal storage element of thecomputing device 1500 (e.g., hard disk drive) are often temporarilyqueued into system memory 1508 prior to their being operated upon by theone or more processor(s) in the implementation of a software program.Similarly, data that a software program determines should be sent fromthe computing device 1500 to an outside entity through one of thecomputing system interfaces, or stored into an internal storage element,is often temporarily queued in system memory 1508 prior to its beingtransmitted or stored.

Further, for example, an ICH, such as ICH 130 of FIG. 1 , may be usedfor ensuring that such data is properly passed between the system memory1508 and its appropriate corresponding computing system interface (andinternal storage device if the computing system is so designed) and mayhave bi-directional point-to-point links between itself and the observedI/O sources/devices 1504. Similarly, an MCH, such as MCH 116 of FIG. 1 ,may be used for managing the various contending requests for systemmemory 1508 accesses amongst CPU 1512 and GPU 1514, interfaces andinternal storage elements that may proximately arise in time withrespect to one another.

I/O sources 1504 may include one or more I/O devices that areimplemented for transferring data to and/or from computing device 1500(e.g., a networking adapter); or, for a large scale non-volatile storagewithin computing device 1500 (e.g., hard disk drive). User input device,including alphanumeric and other keys, may be used to communicateinformation and command selections to GPU 1514. Another type of userinput device is cursor control, such as a mouse, a trackball, atouchscreen, a touchpad, or cursor direction keys to communicatedirection information and command selections to GPU 1514 and to controlcursor movement on the display device. Camera and microphone arrays ofcomputing device 1500 may be employed to observe gestures, record audioand video and to receive and transmit visual and audio commands.

Computing device 1500 may further include network interface(s) toprovide access to a network, such as a LAN, a wide area network (WAN), ametropolitan area network (MAN), a personal area network (PAN),Bluetooth, a cloud network, a mobile network (e.g., 3rd Generation (3G),4th Generation (4G), etc.), an intranet, the Internet, etc. Networkinterface(s) may include, for example, a wireless network interfacehaving antenna, which may represent one or more antenna(e). Networkinterface(s) may also include, for example, a wired network interface tocommunicate with remote devices via network cable, which may be, forexample, an Ethernet cable, a coaxial cable, a fiber optic cable, aserial cable, or a parallel cable.

Network interface(s) may provide access to a LAN, for example, byconforming to IEEE 802.11b and/or IEEE 802.11g standards, and/or thewireless network interface may provide access to a personal areanetwork, for example, by conforming to Bluetooth standards. Otherwireless network interfaces and/or protocols, including previous andsubsequent versions of the standards, may also be supported. In additionto, or instead of, communication via the wireless LAN standards, networkinterface(s) may provide wireless communication using, for example, TimeDivision, Multiple Access (TDMA) protocols, Global Systems for MobileCommunications (GSM) protocols, Code Division, Multiple Access (CDMA)protocols, and/or any other type of wireless communications protocols.

Network interface(s) may include one or more communication interfaces,such as a modem, a network interface card, or other well-known interfacedevices, such as those used for coupling to the Ethernet, token ring, orother types of physical wired or wireless attachments for purposes ofproviding a communication link to support a LAN or a WAN, for example.In this manner, the computer system may also be coupled to a number ofperipheral devices, clients, control surfaces, consoles, or servers viaa conventional network infrastructure, including an Intranet or theInternet, for example.

It is to be appreciated that a lesser or more equipped system than theexample described above may be preferred for certain implementations.Therefore, the configuration of computing device 1500 may vary fromimplementation to implementation depending upon numerous factors, suchas price constraints, performance requirements, technologicalimprovements, or other circumstances. Examples of the computing device1500 may include (without limitation) a mobile device, a personaldigital assistant, a mobile computing device, a smartphone, a cellulartelephone, a handset, a one-way pager, a two-way pager, a messagingdevice, a computer, a personal computer (PC), a desktop computer, alaptop computer, a notebook computer, a handheld computer, a tabletcomputer, a server, a server array or server farm, a web server, anetwork server, an Internet server, a work station, a mini-computer, amain frame computer, a supercomputer, a network appliance, a webappliance, a distributed computing system, multiprocessor systems,processor-based systems, consumer electronics, programmable consumerelectronics, television, digital television, set top box, wirelessaccess point, base station, subscriber station, mobile subscribercenter, radio network controller, router, hub, gateway, bridge, switch,machine, or combinations thereof.

Embodiments may be implemented as any or a combination of: one or moremicrochips or integrated circuits interconnected using a parentboard,hardwired logic, software stored by a memory device and executed by amicroprocessor, firmware, an application specific integrated circuit(ASIC), and/or a field programmable gate array (FPGA). The term “logic”may include, by way of example, software or hardware and/or combinationsof software and hardware.

Embodiments may be provided, for example, as a computer program productwhich may include one or more machine-readable media having storedthereon machine-executable instructions that, when executed by one ormore machines such as a computer, network of computers, or otherelectronic devices, may result in the one or more machines carrying outoperations in accordance with embodiments described herein. Amachine-readable medium may include, but is not limited to, floppydiskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories), andmagneto-optical disks, ROMs, RAMs, EPROMs (Erasable Programmable ReadOnly Memories), EEPROMs (Electrically Erasable Programmable Read OnlyMemories), magnetic or optical cards, flash memory, or other type ofmedia/machine-readable medium suitable for storing machine-executableinstructions.

Moreover, embodiments may be downloaded as a computer program product,wherein the program may be transferred from a remote computer (e.g., aserver) to a requesting computer (e.g., a client) by way of one or moredata signals embodied in and/or modulated by a carrier wave or otherpropagation medium via a communication link (e.g., a modem and/ornetwork connection).

According to various embodiments, graphics workloads may be processed atcomputing device 1500. Depending on the embodiment, the workloads may beprocessed at either CPU 1512 or GPU 1514. In such embodiments, an FPGAis coupled to each processing core included in CPU 1512 and GPU 1514 toaccelerate execution of performance critical loops and free up resourceson the processor core. In other embodiments, different types of fieldprogrammable integrated circuits (e.g., programmable in the field aftermanufacture) may be implemented.

FPGAs have a high performance and power efficiency in executing criticalloops since they are not limited to a core's data access, instructionset architecture (ISA) and microarchitecture limitations (e.g., avoidinginstruction decode and costly data extraction/shuffling/permutation),while having an exclusively workload specific Single instruction,multiple data (SIMD) configuration that may significantly boostperformance. In embodiments featuring latency-critical workloads (e.g.,ray traversal or texture access), efficient latency hiding may beimplemented within the FPGA by providing a higher number of independentcontexts/threads/fibers.

FIGS. 16A & 16B illustrate embodiments of FPGAs coupled to processingcores. FIG. 16A illustrates one embodiment of CPU 1512 having FPGAs 1620coupled to respective cores 1610. For instance, FPGAs 1620(0)-1620(N)are coupled to cores 1610(0)-1120(N), respectively. Accordingly, eachcore includes a small FPGA to enable a core to select a workload kernelto accelerate. A small FPGA per processor core enables FPGAs 1620 to bequickly reprogrammable, thus making it possible to efficiently exchangeFPGA programs/implementations during the lifetime of a workload. In afurther embodiment, a set of one or more FPGAs 1620 may be assigned tosimultaneously handle different tasks. Thus, one or more FPGAs 1620 maybe programmed to execute different kernels, enabling cores 1610 toaccelerate other kernels.

In the CPU embodiment, FPGAs 1620 are coupled as independent agents to acache memory device 1640 coupled to a core 1610. In one embodiment, eachcache memory device 1640 is an L2 cache coupled to a core 1610 (e.g.,similar to the core's L1) in order to maintain a high bandwidth and lowlatency data connection, while keeping all data accesses cache-coherent.Attaching a FPGA 1620 to a core 1610 L2 provides a high bandwidth andvery low latency data access connection, which avoids using FPGAresources to add similar large cache functionality within the FPGA 1620.Accordingly, more space within a FPGA 1610 may be allotted forfunctional units.

For workloads with a high L2 cache hit rate (e.g., >90%), such as raytraversal, the direct L2 connection in combination with 16-32threads/fibers per FPGA 1620 provides a significant performance boost,making a kernel completely throughput-bound. This is a distinction fromthe latency bound result in current software implementations. In afurther embodiment, having the FPGA as a dedicated L2 agent, andtherefore forcing all data transfer through the L2, maintains a validcache-coherence state.

FIG. 16B illustrates an embodiment of GPU 1514 having FPGAs 1620 coupledto respective cores 1610 similar to that shown in FIG. 16A. However, inthe GPU embodiment, each local FPGA 1620 is coupled to a local memory1660 that supports the core 1610. Accordingly, each local FPGA is usedon the shared multiprocessor (SM) level. In one embodiment, the SMs haveseveral shared units (e.g., a shared texture sampler, raster engine,etc.), so that each FPGA 1620 operates with the other shared resourcesby allowing a FPGA 1620 to interact with that SM's local memory andregister file.

FIG. 17A illustrates one embodiment of a core 1610 coupled to a FPGA1620. In one embodiment, core 1610 includes a controller 1710 to controlthe execution of the coupled FPGA 1620. In one embodiment, controller1710 controls a FPGA 1620 via special memory-mapped I/O (MMIO) regions.However in other embodiments, controller 1710 may control a FPGA 1620 bydedicated processor (e.g., x86) instructions. In further embodiments,resources (e.g., page tables, internal memory↔L2 or ring/mesh↔L2 datatransfer queues, etc.) are shared with core 1610.

FIG. 17B illustrates an embodiment in which multiple cores 1610 (e.g.,core 0 and core 1) are coupled to FPGA 1620. In this embodiment,controllers 1710(a) and 1710(b) within core 0 and core 1, respectively,control the execution of the coupled FPGA 1620. In such an embodiment,core 0 and core 1 may share a common last-level cache. Thus, FPGA 1620is coupled to the last-level cache.

The implementation of core local FPGAs 1620 provides for less resourcecontention by enabling the cores to operate independently. Since eachcore may operate independently, the FPGAs 1620 may be more easilyvirtualized and partitioned. For instance, a chip with N cores (eachhaving its own FPGA) may be partitioned to appear as M chips with N/Mcores.

Any use of a particular brand, word, term, phrase, name, and/or acronym,such as “GPU”, “GPU domain”, “GPGPU”, “CPU”, “CPU domain”, “graphicsdriver”, “workload”, “application”, “frame”, “work unit”, “draw”,“dispatch”, “API”, “hardware”, “software”, “agent”, “graphics driver”,“kernel mode graphics driver”, “user-mode driver”, “UMD”, “user-modedriver framework”, “UMDF”, “bits”, “bytes”, “interpolation”, etc.,should not be read to limit embodiments to software or devices thatcarry that label in products or in literature external to this document.

References to “one embodiment”, “an embodiment”, “example embodiment”,“various embodiments”, etc., indicate that the embodiment(s) sodescribed may include particular features, structures, orcharacteristics, but not every embodiment necessarily includes theparticular features, structures, or characteristics. Further, someembodiments may have some, all, or none of the features described forother embodiments.

In the foregoing specification, embodiments have been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of embodiments asset forth in the appended claims. The Specification and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

In the following description and claims, the term “coupled” along withits derivatives, may be used. “Coupled” is used to indicate that two ormore elements co-operate or interact with each other, but they may ormay not have intervening physical or electrical components between them.

As used in the claims, unless otherwise specified the use of the ordinaladjectives “first”, “second”, “third”, etc., to describe a commonelement, merely indicate that different instances of like elements arebeing referred to, and are not intended to imply that the elements sodescribed must be in a given sequence, either temporally, spatially, inranking, or in any other manner.

The following clauses and/or examples pertain to further embodiments orexamples. Specifics in the examples may be used anywhere in one or moreembodiments. The various features of the different embodiments orexamples may be variously combined with some features included andothers excluded to suit a variety of different applications. Examplesmay include subject matter such as a method, means for performing actsof the method, at least one machine-readable medium includinginstructions that, when performed by a machine, cause the machine toperform acts of the method, or of an apparatus or system forfacilitating hybrid communication according to embodiments and examplesdescribed herein.

Some embodiments pertain to Example 1 that includes a processingapparatus, comprising a plurality of processing cores, including a firstprocessing core and a second processing core, a first field programmablegate array (FPGA) coupled to the first processing core to accelerateexecution of workloads processed at the first processing core and asecond FPGA coupled to the second processing core to accelerateexecution of workloads processed at the second processing core.

Example 2 includes the subject matter of Example 1, wherein the firstand second FPGAs accelerate execution of performance critical loops in aworkload.

Example 3 includes the subject matter of Examples 1 and 2, wherein thefirst processing core selects a first workload to be accelerated at thefirst FPGA and the second processing core selects a second workload tobe accelerated at the second FPGA.

Example 4 includes the subject matter of Examples 1-3, wherein the firstFPGA is programmed to execute a first type of workload and the secondFPGA is programmed to execute a second type of workload.

Example 5 includes the subject matter of Examples 1-4, wherein the firstand second FPGAs provide one or more independent threads to performlatency hiding.

Example 6 includes the subject matter of Examples 1-5, wherein the firstprocessing core comprises a first controller to control execution of thefirst FPGA, and the second processing core comprises a second controllerto control execution of the second FPGA.

Example 7 includes the subject matter of Examples 1-6, wherein the firstcontroller and the second controller control execution of the first FPGAand the second FPGA via memory-mapped I/O (MMIO) regions.

Example 8 includes the subject matter of Examples 1-7, wherein the firstcontroller and the second controller control execution of the first FPGAand the second FPGA via dedicated processor instructions.

Example 9 includes the subject matter of Examples 1-8, wherein theprocessing apparatus comprises a general-purpose microprocessor.

Example 10 includes the subject matter of Examples 1-9, furthercomprising a first cache memory device coupled to the first processingcore and the first FPGA and a second cache memory device coupled to thesecond processing core and the second FPGA.

Example 11 includes the subject matter of Examples 1-10, wherein thefirst FPGA is an independent agent to the first cache memory device, andthe second FPGA is an independent agent to the second cache memorydevice.

Example 12 includes the subject matter of Examples 1-11, furthercomprising a third processing core coupled to the first FPGA and a firstcache memory device coupled to the first processing core, the thirdprocessing core and the first FPGA, wherein the first FPGA acceleratesexecution of workloads processed at the first processing core and thethird processing core.

Example 13 includes the subject matter of Examples 1-12, wherein theprocessing apparatus comprises a graphics processing unit (GPU).

Example 14 includes the subject matter of Examples 1-13, furthercomprising a first memory device coupled to the first processing coreand the first FPGA and a second memory device coupled to the secondprocessing core and the second FPGA.

Example 15 includes the subject matter of Examples 1-14, furthercomprising a third processing core coupled to the first FPGA and a firstmemory device coupled to the first processing core, the third processingcore and the first FPGA, wherein the first FPGA accelerates execution ofworkloads processed at the first processing core and the thirdprocessing core.

Some embodiments pertain to Example 16 that includes a centralprocessing unit (CPU), comprising a plurality of processing cores,including a first processing core and a second processing core, a firstfield programmable gate array (FPGA) coupled to the first processingcore to accelerate execution of workloads processed at the firstprocessing core, a first cache memory device coupled to the firstprocessing core and the first FPGA, a second FPGA coupled to the secondprocessing core to accelerate execution of workloads processed at thesecond processing core and a second cache memory device coupled to thesecond processing core and the second FPGA.

Example 17 includes the subject matter of Example 16, wherein the firstprocessing core selects a first workload to be accelerated at the firstFPGA and the second processing core selects a second workload to beaccelerated at the second FPGA.

Example 18 includes the subject matter of Examples 16 and 17, whereinthe first FPGA is programmed to execute a first type of workload and thesecond FPGA is programmed to execute a second type of workload.

Example 19 includes the subject matter of Examples 16-18, wherein thefirst processing core comprises a first controller to control executionof the first FPGA, and the second processing core comprises a secondcontroller to control execution of the second FPGA.

Example 20 includes the subject matter of Examples 16-19, furthercomprising a third processing core coupled to the first FPGA and thefirst cache memory device, wherein the first FPGA accelerates executionof workloads processed at the first processing core and the thirdprocessing core.

Some embodiments pertain to Example 21 that includes a graphicsprocessing unit (GPU), comprising a plurality of graphics processingcores, including a first graphics processing core and a second graphicsprocessing core, a first field programmable gate array (FPGA) coupled tothe first graphics processing core to accelerate execution of graphicsworkloads processed at the first graphics processing core, a firstmemory device coupled to the first graphics processing core and thefirst FPGA, a second FPGA coupled to the second graphics processing coreto accelerate execution of graphics workloads processed at the secondgraphics processing core and a second memory device coupled to thesecond graphics processing core and the second FPGA.

Example 22 includes the subject matter of Example 21, wherein the firstgraphics processing core selects a first workload to be accelerated atthe first FPGA and the second graphics processing core selects a secondworkload to be accelerated at the second FPGA.

Example 23 includes the subject matter of Examples 21 and 22, whereinthe first FPGA is programmed to execute a first type of graphicsworkload and the second FPGA is programmed to execute a second type ofgraphics workload.

Example 24 includes the subject matter of Examples 21-23, wherein thefirst graphics processing core comprises a first controller to controlexecution of the first FPGA, and the second graphics processing corecomprises a second controller to control execution of the second FPGA.

Example 25 includes the subject matter of Examples 21-24, furthercomprising a third graphics processing core coupled to the first FPGAand the first memory device, wherein the first FPGA acceleratesexecution of workloads processed at the first graphics processing coreand the third graphics processing core.

The drawings and the forgoing description give examples of embodiments.Those skilled in the art will appreciate that one or more of thedescribed elements may well be combined into a single functionalelement. Alternatively, certain elements may be split into multiplefunctional elements. Elements from one embodiment may be added toanother embodiment. For example, orders of processes described hereinmay be changed and are not limited to the manner described herein.Moreover, the actions of any flow diagram need not be implemented in theorder shown; nor do all of the acts necessarily need to be performed.Also, those acts that are not dependent on other acts may be performedin parallel with the other acts. The scope of embodiments is by no meanslimited by these specific examples. Numerous variations, whetherexplicitly given in the specification or not, such as differences instructure, dimension, and use of material, are possible. The scope ofembodiments is at least as broad as given by the following claims.

What is claimed is:
 1. An apparatus comprising: a processor including aplurality of processor cores, the processor including: a first processorcore to process a first plurality of threads; a second processor core toprocess a second plurality of threads; and a cache memory coupled to thefirst processor core and the second processor core; and a fieldprogrammable gate array (FPGA) coupled to or included within theprocessor, the FPGA configurable to share a register file with the firstprocessor core-of and the second processor core, and configurable toaccelerate execution of workloads processed at the first processor coreor the second processor core.
 2. The apparatus as in claim 1, whereinthe FPGA is an independent agent to the cache memory.
 3. The apparatusas in claim 1, wherein the first processor core or the second processorcore is a graphics processor core.
 4. The apparatus as in claim 1,wherein the first processor core and the second processor core includean integer unit and a floating point unit.
 5. The apparatus as in claim4, wherein the register file includes a register configured to store aninteger data type and a register configured to store a floating pointdata type.
 6. The apparatus as in claim 5, wherein the first processorcore is a central processing unit and the second processor core is agraphics processing unit.
 7. The apparatus as in claim 5, wherein thefirst processor core and the second processor core each include acontroller coupled with the FPGA, the first processor core and thesecond processor core to control execution of the FPGA via thecontroller.
 8. A method comprising: processing a first plurality ofthreads via a first processor core of a processor including a pluralityof processor cores; processing a second plurality of threads via asecond processor core of the processor; while processing the firstplurality of threads and the second plurality of threads, reading a setof data from a register file coupled with the first processor core, thesecond processor core, and a field programmable gate array (FPGA);accelerating, via first data in the set of data, a first workloadprocessed by the first plurality of threads via the FPGA; andaccelerating, via second data in the set of data, a second workloadprocessed by the second plurality of threads via the FPGA.
 9. The methodas in claim 8, further comprising selecting, by the first processorcore, the first workload to be accelerated at the FPGA and selecting, bythe second processor core, the second workload to be accelerated at theFPGA.
 10. The method as in claim 8, further comprising programming logicgates of the FPGA to execute a first type of workload, the first type ofworkload associated with the first workload and the second workload. 11.The method as in claim 10, further comprising programming logic gates ofthe FPGA to execute a second type of workload, the second type ofworkload associated with a third workload to be accelerated by the FPGA.12. The method as in claim 10, further comprising reprogramming thelogic gates of the FPGA during acceleration of the first workload orreprogramming the logic gates of the FPGA during acceleration of thesecond workload.
 13. A data processing system comprising: a peripheralbus interconnect; a memory device; and a processor coupled with thememory device and the peripheral bus interconnect, the processorincluding: a first processor core to process a first plurality ofthreads; a second processor core to process a second plurality ofthreads; and a cache memory coupled to the first processor core and thesecond processor core; and a field programmable gate array (FPGA)coupled to the first processor core and the second processor core, theFPGA configurable to share a register file with the first processor coreand the second processor core, and configurable to accelerate executionof workloads processed at the first processor core or the secondprocessor core.
 14. The data processing system as in claim 13, whereinthe FPGA is an independent agent to the cache memory.
 15. The dataprocessing system as in claim 13, wherein the first processor core andthe second processor core include an integer unit and a floating pointunit and the register includes a register configured to store an integerdata type and a register configured to store a floating point data type.16. The data processing system as in claim 15, wherein the firstprocessor core or the second processor core is a graphics processorcore.
 17. The data processing system as in claim 15, wherein the firstprocessor core is a central processing unit and the second processorcore is a graphics processing unit.
 18. The data processing system as inclaim 15, wherein the FPGA is configurable to share a register file withthe first processor core and the second processor core.